Chips and integrated circuits are crucial hardware foundations of the modern information world. To facilitate chips to exchange signals with other circuits (e.g., other chips/dies, integrated circuits and/or printed circuit boards) as well as acquiring operating electric power, the chips are provided with input/output (IO) units as interfaces for bridging externally.
Each IO unit in a chip is provided generally with a single pad, which connects to other external circuits via corresponding signal wires or electrical wires (e.g., traces) in the conventional structures. Since each IO unit is only configured with one predetermined function at a time, it is necessary that the chip of the prior art be provided with IO units of different structures to respectively perform corresponding functions. For example, certain IO units are capable of signal driving and signal receiving, whereas certain IO units are dedicated for coupling to predetermined voltages (e.g., operation voltage or ground) so that the chip acquires needed operating power.
Apart from the need of distinguishing the IO units according to their functionalities, pads of neighboring IO units are placed in a staggered arrangement for reducing a size of the chip, further demanding that IO units at different positions require different structures. More specifically, even though functions of two IO units might be the same, the structures of the two IO units are bound to be different in order to place corresponding pads of the two IO units in a staggered arrangement. During the design of a chip, the various factors described above may lead to difficulties in automatic placement and routing of the IO units with the conventional structures, so that placement and routing of the IO units are performed manually, thus increasing time and cost need for the chip design.
Further, the foregoing single-pad/single-function IO units lack design and application flexibilities—to realize chips that are adaptable to different interfaces, re-design and re-arrangement of the IO units are needed to satisfy requirements of different interfaces to again add time and cost on such customization. Yet, IO units achieved through the above procedures are incapable of better contributing to integration of the pads, resulting in inapplicability of the IO units when the number of IO units is limited.